How do I toggle a sample clock every n clock cycles?

I am new to Verilog, so I am not sure how to go about doing this. I have a clock, 'samp_clk', that toggles every 10 clock cycles of the system clock, 'clock' (or that's what I tried to do). This is what I have so far:

 //'counter' counts the number of rising edges for system clock //'samp_clk' is the sample clock, 'clock' is system clock always @ (posedge clock)begin if(~reset)begin if(counter == 10)begin samp_clk


The way I wrote it, I feel like my samp_clk will only stay asserted for one clock cycle. How can I make it so that it toggles between 1 and 0 every ten clock cycles?
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asked Dec 2, 2015 at 0:05
user5620123 user5620123
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3 Answers 3
 if(counter == 10)begin samp_clk  

This will result to 11 clock cycles since we start counting from 0 to 10.
First step, define a counter wherein it resets to a certain number (clock cycles). For example, you want to detect 10 clock cycles (n = 10), when counter is more than or equal to 9, it sets back to 0.
 always @ (posedge clk)begin if(~reset)begin counter = 9)begin counter  

Then simply, toggle samp_clk based from the counter when it's equal to n-1 (10 - 1 = 9).
always @(posedge clk) begin if (~reset) begin samp_clk  

Notice that I've separated two flip-flops to make debugging easy and clear enough to understand its logic.
Here is the code with a test bench included.
module ten_clock(input clk, reset, output reg samp_clk); reg [7:0] counter; //'counter' counts the number of rising edges for system clock always @ (posedge clk)begin if(~reset)begin counter  

You can try to run this code and see the wave form if this behavior is what you expect.

answered Dec 2, 2015 at 0:45
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You want to toggle it, so toggle it.
Also note that to toggle every 10 clocks, you will have to set your counter to 0 when its value is 10-1.
Try this (not tested):
//'counter' counts the number of rising edge s for system clock //'samp_clk' is the sample clock, 'clock' is sy stem clock always @ (posedge clock)begin if(~reset)begin if(counter == 9)begin samp_clk  

answered Dec 2, 2015 at 0:20
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Since you added the reset logic: you should set counter to 0 in the reset as well.
Commented Dec 2, 2015 at 0:22
You are correct, this code sets samp_clk to be 1 when the counter is 10 and otherwise sets it to 0 . This means you will have a signal which is asserted for 1 clock cycle and low for 10 clock cycles. The basic logic is correct (count for 10 clock cycles) but the value given to samp_clk is incorrect.
What you want to have is that samp_clk is the same value as it was in the previous cycle if counter ins't 10 and to flip samp_clk when it is. To flip a signal you want to assign the signal to the inverse of a signal: samp_clk 
After you have that working you might need to refactor your code because I think it is going to produce latches in its current state.
answered Dec 2, 2015 at 0:20
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Actually, count would be 11 clock cycles when counter reaches 10 since we start counting the number of clock cycles from 0. I was caught by off-by-one error (OBOE) too and noticed the bug until I run the actual simulation.
Commented Dec 2, 2015 at 1:10
@e19293001: since this looks very much like a beginner question/homework I wasn't answering everything but pointing them in the right direction. They were using counter=10 in their example code, so I just copied. And then they'll work out for themselves that they have an off by one error.